Hi Hacktarux,
Right now, I'm more focused on modeling flow and control... not so much with the timings. That being said, I do have the means for creating the delays in place already (see the beginning of CycleVR4300, for example). Essentially, each device is responsible for managing its own delays, and broadcasting information about those delays to other components as needed. The former is done within each plugin itself (perhaps the VR4300 is stalling on full write buffers), and the latter is communicated through the bus component (an RDRAM occured, now how long should the requesting device wait until it actually "receives" that data). In some ways, I've basically separated emulation and simulation, and use the simulated statistics to drive the emulation.
I'm waiting on the timings due to the amount of complexity involved in just modeling the pipeline itself. Properly modeling the flushing of the pipeline on an external interrupt , for example, gave me a royal headache... and I didn't even have to deal with timings at the time! I'm also hoping that adding in the delays will give me a performance boost... after all, the ultimate goal of my project is to have a simulator that can play games in realtime and debunk the "LLE is too slow" myth once and for all!
Glad to see you're still interested in the project as well... I was following your project closely before I started mine -- I got a lot of my inspiration from you! PS: I know you said you were waiting to release the source until it's ready -- if you would be willing to share it, I would be more than willing to respect any wishes that you have to keep it closed. It would be great to have another reference, as you seem to have the PIF and timings hammered down better than I currently do.
Cool! I think that one jagged line that you see there is due to another bug that I'm currently tracking down... I believe this is the same bug that is preventing commercial ROMs from rendering properly and causing input/PIF issues in some areas.