Most of the way through the core rewrite, things are shaping up:
Still need timings for almost all components, as well as RSP/RDP fixes and rewrites. The intricacies of the cycle-accurate pipelines are proving to be quite the challenges.
Anyone have any idea how many cycles it takes to write to memory mapped registers (roughly)? Does the VR4300 just have to synchronize to the RCP bus clock and the memory-mapped registers will capture the value immediately, or is there some delay involved like RAM?
I'm guessing I'll need the...
I'd like to inform the community that I have been developing a cycle-accurate emulator for the N64 (not to steal from Hackturax's fire)! The project is currently in infant stages, and nameless, but has several goals:
The community has yet to see a cycle-accurate emulator for...