Based on the HALT documentation in Pan docs, when interrupts are not enabled, in section 2.7.3 (Low Power mode), after HALT, the DMG cpu should repeat the next command for one time. Looking at the execution of Blargg's CPU instruction test 2 individual rom in BGB, it seems that the PC register is stalled, until a timer interrupt is on, even though interrupts are NOT enabled. Now comparing theory to practice, it seems there is a great difference from what I've understood reading pan docs. Am I missing something? I mean a step by step execution of the individual Blargg's rom should be like this?:
What on earth a real DMG does in this situation?
Starting from PC = 0xC363
$C363 | LD a, 05
$C365 | LD (FF07), a
$C367 | LD a, 0
$C369 | LD (FF05), a ; timer becomes zero
$C36B | LD a, 0 ; (TIMA = 1)
$C36D | LD (FF0F), a ; IF is now zero.
$C36F | HALT (TIMA = 1)
$C370 | NOP ; I've seen many things here. BGB stalls until timer overflows. A somewhat known open source emulator enables a timer interrupt flag at this point...
$C370 | NOP ; <--- Based on the docs shouldn't just this happen when IME isn't set? (TIMA = 3)
$C371 | LD a, (FF0F)
$C373 | AND a, 04 ; During those instructions could a timer interrupt flag be enabled?